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MPC106 PCIB/MC User's Manual
MOTOROLA
Organization
Following is a summary and a brief description of the major sections of this manual:
Chapter 1, “Overview,” is useful for readers who want a general understanding of
the features and functions of the MPC106.
Chapter 2, “Signal Descriptions,” provides descriptions of individual signals of the
MPC106.
Chapter 3, “Device Programming,” is useful for software engineers who need to
understand the address space and functionality of the registers implemented in the
MPC106.
Chapter 4, “Processor Bus Interface,” describes the interaction between the
MPC106 and the 60x processor or multiple 60x processors.
Chapter 5, “Secondary Cache Interface,” describes the operation of the secondary or
level 2 (L2) cache interface.
Chapter 6, “Memory Interface,” provides details for interfacing the MPC106 to
DRAM, EDO, SDRAM, ROM, and Flash ROM devices.
Chapter 7, “PCI Bus Interface,”describes the MPC106 as a bridge from the 60x
processor bus to the PCI bus and the MPC106 as a PCI agent.
Chapter 8, “Internal Control,” describes the internal buffers between the interfaces
of the MPC106.
Chapter 9, “Error Handling,” describes how the MPC106 handles error detection
and reporting on the three primary interfaces—processor interface, memory
interface, and PCI interface.
Appendix A, “Power Management,”provides information about power saving
modes for the MPC106.
Appendix B, “Bit and Byte Ordering,” describes big- and little-endian byte ordering
and the implications on systems using the MPC106.
Appendix C, “JTAG/Testing Support,” describes the IEEE 1149.1 functions used for
facilitating board testing and chip debug.
Appendix D, “Initialization Example,” provides sample initialization code in
PowerPC assembly language.
This manual also includes a glossary and an index.
In this document, the terms ‘601’, ‘603’, and ‘604’ are used as abbreviations for ‘PowerPC
601 microprocessor’, ‘PowerPC 603 microprocessor’, and ‘PowerPC 604 microprocessor’,
respectively.