MOTOROLA
Appendix A. Power Management
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Appendix A
Power Management
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The MPC106 provides the system designer hardware resources to flexibly reduce system
power consumption through the use of software and system hardware power control
mechanisms. This appendix describes the hardware support provided by the MPC106 for
power management.
A.1 MPC106 Power Modes
The MPC106 implements four levels of power reduction—doze, nap, sleep, and suspend,
with power consumption reduced with each step from doze to suspend. The doze, nap, and
sleep modes are entered through software setting the required configuration register bit in
the power management configuration register (PMCR). For more information about this
register, see Section 3.2.4, “Power Management Configuration Registers (PMCRs).” The
suspend mode is entered by the assertion of the SUSPEND signal, as described in
Section 2.2.6.6, “Suspend (SUSPEND)—Input.” All of the power management modes are
enabled by the configuration of the global power management bit, PMCR[PM].
A.1.1 MPC106 Power Mode Transition
While the doze, nap, and sleep modes are enabled by setting the corresponding bits in the
PMCR, in the case of the nap and sleep modes the power management mode is entered upon
the assertion of the QREQ signal. The MPC106 responds by entering the power
management mode selected, and asserts QACK to signal to the processor that the power
management mode has been entered. The doze mode is entered directly by configuring the
doze bit in the PMCR, and does not require the assertion of QREQ.
The configuration of the MPC106 and the processor signals asserted differ depending on
which processor (PowerPC 601 microprocessor, PowerPC 603 microprocessor, or
PowerPC 604 microprocessor) the MPC106 is connected to. The response of the MPC106
is configured through the setting of the processor type bits in PICR1[PROC_TYPE].