MOTOROLA
Chapter 3. Device Programming
3-27
12
LP_REF_EN
0
Low-power refresh
0
Indicates that the MPC106 does not perform memory refresh
cycles when it is in sleep or suspend mode
1
Indicates that the MPC106 continues to perform memory
refresh cycles when in sleep or suspend mode
11
NO_604_RUN
0
When both a PowerPC 604 microprocessor and the MPC106
are in nap mode and the MPC106 is woken up by a PCI
transaction that accesses system memory, this bit controls
whether the MPC106 asserts the QACK signal so the 604 can
respond to the snoop (QACK is connected to the RUN signal on
the 604). Note that the MPC106 ignores NO_604_RUN unless
PICR1[PROC_TYPE] = 0b11, indicating a 604.
0
Indicates that the MPC106 asserts the QACK signal
1
Indicates that the MPC106 does not assert the QACK signal
10
601_NEED_QREQ
0
Indicates whether the MPC106 should use the QREQ signal as
one of the conditions for entering the nap/sleep state when a
PowerPC 601 microprocessor is used in the system. Note that
the MPC106 ignores 601_NEED_QREQ unless
PICR1[PROC_TYPE] = 0b00, indicating a 601.
0
Indicates that the QREQ signal is not required
1
Indicates that the QREQ signal is required
9
SUSP_QACK
0
Indicates whether the MPC106 asserts the QACK signal when
entering the suspend power saving mode.
0
Indicates that the MPC106 does not assert the QACK signal
when entering the suspend power saving mode
1
Indicates that the MPC106 asserts QACK when entering the
suspend power saving mode
8
—
0
This bit is reserved.
7
PM
0
Power management enable
0
Disables the power management logic within the MPC106
1
Enables the power management logic within the MPC106
6
—
0
This bit is reserved.
5
DOZE
0
Enables/disables the doze mode capability of the MPC106. Note
that this bit is only valid if MPC106 power management is enabled
(PMCR1[PM] = 1).
0
Disables the doze mode
1
Enables the doze mode
4
NAP
0
Enables/disables the nap mode capability of the MPC106. Note
that this bit is only valid if MPC106 power management is enabled
(PMCR1[PM] = 1).
0
Disables the nap mode
1
Enables the nap mode
Table 3-14. Bit Settings for Power Management Configuration
Register 1—0x70 (Continued)
Bit
Name
Reset
Value
Description