
xii
MPC106 PCIB/MC User’s Manual
MOTOROLA
CONTENTS
Paragraph
Number
Title
Page
Number
7.5.5
7.6
7.6.1
7.6.2
7.7
7.7.1
7.7.2
7.8
7.8.1
7.8.2
7.8.3
7.8.4
7.9
Exclusive Access and the MPC106...............................................................7-24
PCI Error Functions...........................................................................................7-25
PCI Parity.......................................................................................................7-25
Error Reporting..............................................................................................7-26
MPC106-Implemented PCI Sideband Signals...................................................7-26
ISA_MASTER...............................................................................................7-26
FLSHREQ and MEMACK............................................................................7-27
Emulation Support.............................................................................................7-27
PCI Address Decoding...................................................................................7-27
Interrupt Vector Relocation...........................................................................7-28
Modified Memory Status Register.................................................................7-28
Curious Code Protection................................................................................7-31
Processor-to-PCI Transaction Examples ...........................................................7-31
Chapter 8
Internal Control
8.1
8.1.1
8.1.2
8.1.2.1
8.1.2.2
8.1.3
8.1.3.1
8.1.3.1.1
8.1.3.2
8.2
Internal Buffers....................................................................................................8-1
60x Processor/System Memory Buffers..........................................................8-2
60x Processor/PCI Buffers...............................................................................8-3
Processor-to-PCI-Read Buffer (PRPRB).....................................................8-4
Processor-to-PCI-Write Buffers (PRPWBs)................................................8-5
PCI/System Memory Buffers...........................................................................8-5
PCI-to-System-Memory-Read Buffer (PCMRB)........................................8-7
Speculative PCI Reads from System Memory........................................8-7
PCI-to-System-Memory-Write Buffers (PCMWBs)...................................8-8
Internal Arbitration..............................................................................................8-9
Chapter 9
Error Handling
9.1
9.2
9.2.1
9.2.2
9.2.2.1
9.2.2.2
9.2.3
9.2.3.1
9.2.3.2
9.2.3.3
9.3
9.3.1
Priority of Externally-Generated Interrupts.........................................................9-2
Interrupt and Error Signals...................................................................................9-3
System Reset....................................................................................................9-3
60x Processor Bus Error Signals .....................................................................9-3
Machine Check (MCP)................................................................................9-3
Transfer Error Acknowledge (TEA)............................................................9-4
PCI Bus Error Signals......................................................................................9-5
System Error (SERR) ..................................................................................9-5
Parity Error (PERR).....................................................................................9-5
Nonmaskable Interrupt (NMI).....................................................................9-5
Error Reporting....................................................................................................9-6
60x Processor Interface....................................................................................9-6