
MOTOROLA
Glossary of Terms and Abbreviations
Glossary-3
Fetch
. Retrieving instructions from either the
cache
or main memory and
placing them into the instruction queue.
Flush
. An operation that causes a modified
cache line
to be invalidated and
the data to be written to memory.
Implementation
. A particular processor that conforms to the PowerPC
architecture, but may differ from other architecture-compliant
implementations for example in design, feature set, and
implementation of
optional
features. The PowerPC architecture has
many different implementations.
In-order.
An aspect of an operation that adheres to a sequential model. An
operation is said to be performed in-order if, at the time that it is
performed, it is known to be required by the sequential execution
model.
See
Out-of-order.
Interrupt
. An external signal that causes the 60x to suspend current
execution and take a predefined exception.
Kill
. An operation that causes a
cache line
to be invalidated.
L1 cache.
See
Primary cache.
L2 cache
.
See
Secondary cache.
Latency
. The number of clock cycles necessary to execute an instruction and
make ready the results of that instruction.
Least-significant byte (LSB)
. The byte of least value in an address, register,
data element, or instruction encoding.
Little-endian
. A byte-ordering method in memory where the address
n
of a
word
corresponds to the
least-significant byte
. In an addressed
memory word, the bytes are ordered (left to right) 3, 2, 1, 0, with 3
being the
most-significant byte
.
See
Big-endian.
Most-significant bit (msb)
. The highest-order bit in an address, registers,
data element, or instruction encoding.
Most-significant byte (MSB)
. The highest-order byte in an address,
registers, data element, or instruction encoding.
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