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MPC106 PCIB/MC User's Manual
MOTOROLA
assertion of the MCP signal by setting the PICR1[MCP_EN] bit. If the TEA_EN bit is not
enabled, the data tenure will be terminated by the appropriate number of TA assertions, but
the data transferred will be corrupted.
The assertion of the TEA signal is only sampled by the processor during the data tenure of
the bus transaction, so the MPC106 ensures that the 60x processor receives a qualified data
bus grant by asserting the DBG
n
signal before asserting TEA. The data tenure is terminated
by a single assertion of TEA regardless of whether the data tenure is single-beat or burst.
This sequence is shown in Figure 4-9. In Figure 4-9 the data bus is busy at the beginning of
the transaction, thus delaying the assertion of DBG
n
. Note that although DBB is not an
input to the MPC106, the state of the bus is always known because the MPC106 controls
the data bus grants and either drives or monitors the termination signals.
Figure 4-9. Data Tenure Terminated by Assertion of TEA
The bus transactions interpreted by the MPC106 as bus errors are as follows:
Direct-store transactions, as indicated by the assertion of XATS and TT[0–4]
Any graphics read/write transactions (caused by
eciwx
or
ecowx
instructions)
Write operations into INTA space, 0xBFFF_FFF0 in address map A, or
0xFEFX_XXXX in address map B.
Write operations into ROM or write to Flash ROM if Flash ROM is not enabled, or
if the transfer bus width does not match the Flash ROM data width, or transaction is
not caching-inhibited or write-through. Caching-inhibited or write-through writes to
Flash ROM are the only transactions allowed.
Processor read operation from PCI transaction which is target-aborted by the PCI
target, or if the target asserts PERR.
60x Bus Clock
TS
AACK
60x Address
DBGn
DBB
TA
60x Data
TEA