MOTOROLA
Illustrations
xv
ILLUSTRATIONS
Figure
Number
Title
Page
Number
1-1
2-1
2-2
3-1
3-2
3-3
3-4
3-5
3-6
3-7
3-8
3-9
3-10
3-11
3-12
3-13
3-14
3-15
3-16
3-17
3-18
3-19
3-20
3-21
3-22
3-23
3-24
3-25
3-26
3-27
3-28
3-29
3-30
3-31
3-32
3-33
MPC106 Block Diagram........................................................................................1-2
MPC106 Signal Groupings.....................................................................................2-2
SYSCLK Input with Internal Multiples...............................................................2-45
Address Map A (Contiguous Map)........................................................................3-4
Address Map A (Discontiguous Map) ...................................................................3-5
PCI Memory Map (Address Map A)......................................................................3-6
PCI I/O Map (Address Map A)..............................................................................3-7
Address Map B.....................................................................................................3-10
Emulation Mode Address Map ............................................................................3-14
MPC106 Configuration Space .............................................................................3-21
PCI Command Register........................................................................................3-23
PCI Status Register...............................................................................................3-25
Power Management Configuration Register 1 (PMCR1)....................................3-26
Power Management Configuration Register 2 (PMCR2)....................................3-28
ECC Single-Bit Error Counter Register—0xB8 ..................................................3-29
ECC Single-Bit Error Trigger Register—0xB9...................................................3-29
Error Enabling Register 1 (ErrEnR1)...................................................................3-30
Error Enabling Register 2 (ErrEnR2)...................................................................3-31
Error Detection Register 1 (ErrDR1)—0xC1.......................................................3-32
Error Detection register 2 (ErrDR2)—0xC5........................................................3-33
60x Bus Error Status Register—0xC3 .................................................................3-34
PCI Bus Error Status Register—0xC7.................................................................3-35
60x/PCI Error Address Register—0xC8..............................................................3-35
Memory Starting Address Register 1—0x80.......................................................3-36
Memory Starting Address Register 2—0x84.......................................................3-37
Extended Memory Starting Address Register 1—0x88.......................................3-37
Extended Memory Starting Address Register 2—0x8C......................................3-37
Memory Ending Address Register 1—0x90........................................................3-38
Memory Ending Address Register 2—0x94........................................................3-38
Extended Memory Ending Address Register 1—0x98........................................3-39
Extended Memory Ending Address Register 2—0x9C .......................................3-39
Memory Bank Enable Register—0xA0 ...............................................................3-40
Memory Page Mode Register—0xA3..................................................................3-41
Memory Control Configuration Register 1 (MCCR1)—0xF0.............................3-42
Memory Control Configuration Register 2 (MCCR2)—0xF4.............................3-45
Memory Control Configuration Register 3 (MCCR3)—0xF8.............................3-46