MOTOROLA
Chapter 4. Processor Bus Interface
4-13
4.3.2.2 TBST and TSIZ[0–2] Signals and Size of Transfer
The transfer size (TSIZ[0–2]) signals, in conjunction with the transfer burst (TBST) signal,
indicate the size of the requested data transfer, as shown in Table 4-3. These signals may be
used along with address bits A[29–31] to determine which portion of the data bus contains
valid data for a write transaction or which portion of the bus should contain valid data for
a read transaction. The 60x processors use the eight-word burst transactions for the transfer
of cache blocks. For these transactions, the TSIZ[0–2] signals are encoded as 0b010, and
address bits A[27–28] determine which double-word transfer should occur first.
The MPC106 supports critical-word-first burst transactions (double-word–aligned) from
the 60x processor. The MPC106 transfers this double word of data first, followed by double
words from increasing addresses, wrapping back to the beginning of the eight-word block
as required.
Table 4-2. Transfer Type Encodings Generated by the MPC106
TT[0–4]
(Driven by MPC106)
60x Bus Operation
Condition
00010
Burst-write-with-flush
Generated in response to nonlocked PCI writes to
memory
10010
Burst-write-with-flush-atomic
Generated in response to locked PCI writes to memory
00110
Burst-write-with-kill
Generated in response to nonlocked/locked PCI writes
with invalidate to memory
11110
Burst-RWITM-atomic
Read-with-intent-to-modify—generated for locked PCI
reads
01010
Burst-read
Generated in response to nonlocked PCI reads to
memory
Table 4-3. MPC106 Transfer Size Encodings
TBST
TSIZ0
TSIZ1
TSIZ2
Transfer Size
Asserted
0
1
0
Eight-word burst
Negated
0
0
0
Eight bytes
Negated
0
0
1
One byte
Negated
0
1
0
Two bytes
Negated
0
1
1
Three bytes
Negated
1
0
0
Four bytes
Negated
1
0
1
Five bytes
Negated
1
1
0
Six bytes
Negated
1
1
1
Seven bytes