MOTOROLA
Chapter 3. Device Programming
3-55
5
LE_MODE
0
This bit controls the endian mode of the MPC106. Note that this bit
is also accessible from the external configuration register at 0x092.
See Appendix B, “Bit and Byte Ordering,” for more information.
0
Big-endian mode
1
Little-endian mode
4
CF_LOOP_SNOOP
1
This bit causes the MPC106 to repeat a snoop operation (due to a
PCI-to-memory transaction) until it is not retried (ARTRY input
asserted) by the processor(s) or the L2 cache. Generally, this bit
indicates whether the system implements snoop looping using the
high-priority snoop request (HP_SNP_REQ) signal on the 601. See
PowerPC 601 RISC Microprocessor User’s Manualfor more
information.
0
Snoop looping is disabled
1
Snoop looping is enabled
3
CF_APARK
0
This bit indicates whether the 60x address bus is parked. See
Section 4.3.1, “Address Arbitration,” for more information.
0
Indicates that no processor is parked on the 60x address bus
1
Indicates that the last processor that used the 60x address bus
is parked on the 60x address bus
2
Speculative PCI
Reads
0
This bit controls speculative PCI reads from memory. Note that the
MPC106 performs a speculative read in response to a PCI
read-multiple command, even if this bit is cleared.
See Chapter 8, “Internal Control,” for more information.
0
Indicates that speculative reads are disabled.
1
Indicates that speculative reads are enabled.
1–0
CF_L2_MP
00
L2/multiprocessor configuration. These bits in conjunction with
CF_EXTERNAL_L2, indicate the processor and L2 configuration of
the system. See Table 3-36 for the specific bit encodings. See
Section 5.4, “L2 Cache Interface Parameters,” for more information.
Table 3-35. Bit Settings for PICR1—0xA8 (Continued)
Bit
Name
Reset
Value
Description