
6-26
MPC106 PCIB/MC User's Manual
MOTOROLA
6.3.10 DRAM/EDO Refresh
The memory interface supplies CAS before RAS (CBR) refreshes to DRAM/EDO
according to the refresh interval, MCCR2[REFINT]. The value stored in REFINT
represents the number of 60x bus clock cycles required between CBR refreshes. The value
for REFINT depends on the specific DRAM/EDOs used and the operating frequency of the
MPC106. The value should allow for any potential collisions between DRAM/EDO
accesses and refresh cycles. The period of the refresh interval must be greater than the
access time to insure that read and write operations complete successfully.
If a burst read is in progress at the time a refresh operation is to be performed, the refresh
waits for the read to complete. In the worst case, the refresh must wait the number of clock
cycles required by the longest programmed access time. The value stored to REFINT
should be the number of clock cycles between row refreshes reduced by the number of
clock cycles required by the longest access time (to allow for potential collisions).
For example, given a DRAM with 4096 rows and a cell refresh time of 64 ms, the number
of clocks between row refreshes would be 64 ms
÷
4096 rows = 15.6
μ
s. If the 60x bus clock
is running at 66 MHz, the number of clock cycles per row refresh is 15.6
μ
s
x
66 MHz =
1030 clock cycles. If the number of clock cycles for the longest burst access time is 24
clocks, then the value stored in REFINT would be 0b00_0011_1110_1110 (in decimal,
1030 – 24 = 1006).
6.3.10.1 DRAM/EDO Refresh Timing
The refresh timing for DRAM/EDO is controlled by the programmable timing parameter
MCCR3[RAS
6P
]. RAS
6P
determines the number of 60x bus clock cycles that RAS is held
asserted during a CBR refresh. The MPC106 implements bank staggering for CBR
refreshes, as shown in Figure 6-14; see Table 6-5 for the acronyms used in Figure 6-14. The
acronyms with subscripted numbers represent the programmable timing parameters of the
MPC106.