
A-2
MPC106 PCIB/MC User's Manual
MOTOROLA
In a system designed using the 601, the MPC106 can be configured to ignore the state of
the QREQ signal, and enters the nap or sleep mode directly upon the setting of the required
PMCR bits. This is controlled through PMCR[601_NEED_QREQ], which when cleared to
0 allows the immediate invocation of the nap or sleep mode without assertion of QREQ,
and when set to 1 requires the assertion of QREQ by system power control logic to enter
the desired power management mode.
In systems designed using the 603, the power control signals QREQ and QACK are
connected to the corresponding signals on the MPC106, and the doze, nap, or sleep mode
is entered following the configuration of the required bit in the PMCR, and the assertion of
QREQ (in nap and sleep modes) to the MPC106 by the 603.
In systems designed using the 604, the MPC106’s QREQ signal is connected to the 604’s
HALT signal, and the MPC106’s QACK signal is connected to the 604’s RUN signal, and
the doze, nap, or sleep mode is entered following the configuration of the required bit in the
PMCR, and the assertion of QREQ (in nap and sleep modes) to the MPC106 by the 604.
Configuring the processor type bits in PICR1[PROC_TYPE] for the 604 causes the signal
levels sampled and driven by the MPC106’s QREQ and QACK signals to correspond to the
levels required by the 604’s RUN and HALT signals.
Figure A-1 shows the five power modes of the MPC106, and the conditions required for
entering and exiting those modes.
Figure A-1. MPC106 Power Modes
Doze
T1: PMCR[DOZE]) = 1 & PMCR[PM] =1
T2: hard reset, BRx = 0, PCI address hit, NMI
T3: PMCR[NAP]=1 & PMCR[PM] =1 & QREQ = 0 (or HALT = 1 in 604 system)
T4: hard reset, BRx = 0, PCI address hit, NMI
T5: PMCR[SLEEP] = 1 & PMCR[PM] = 1 & QREQ = 0 (or HALT = 1 in 604 system)
T6: hard reset, BRx = 0, NMI
T7: suspend = 0 & PMCR[PM] =1
T8: suspend = 1
Suspend
T1
T2
T3
T4
T5
T6
T7
T8
Full-On
Sleep
Nap