MOTOROLA
Appendix D. Initialization Example
D-3
;#
lis r3, MPC106_REG # start building new register number
ori r3, r3, PICR2 # register number 0xac
stwbrx r3, 0, r1 # write this value to CONFIG_ADDR
lwbrx r4, 0, r2 # load r4 from CONFIG_DATA
lis r0, 0x2800 # Reserved bits are 29, 27, and 11
ori r0, r0, 0x0800 # bit 31 is MSb, bit 0 is LSb
and r4, r4, r0 # clears all 0xac reg except reserved bits
;# lis r0, 0x800f #flow through type
;# lis r0, 0x814f #pipelined type, fast l2 mode
lis r0, 0x804f #pipelined type, slow l2 mode
;# ori r0, r0, 0x068e #1 bank 256 k
;# ori r0, r0, 0x068f #1 bank 256 k with adsp mode on
;# ori r0, r0, 0x069e #2 banks 512 k, fast castout, aphase = 3 wait
#hit delay =3
ori r0, r0, 0x0296 #2 banks 512 k, fast castout, aphase = 1 wait
#hit delay=1
or r4, r4, r0 # sets the desired bits
stwbrx r4, 0, r2 # write value to CONFIG_DATA
;# These next five lines may not be necessary if the above OR pattern = 0x c29e 650e
lwbrx r4, 0, r2
lis r0, 0x4000 # Now that we've written to the 0x ac register,
ori r0, r0, 0x4000 # keep pattern the same, but set the L2_EN bit (see next reg)
or r4, r4, r0 # by setting bit 30 to a 1
stwbrx r4, 0, r2 # write value to CONFIG_DATA
;#
lis r3, MPC106_REG # start building new register number
ori r3, r3, PICR1 # register number 0xa8
stwbrx r3, 0, r1 # write this value to CONFIG_ADDR
lwbrx r4, 0, r2 # load r4 from CONFIG_DATA
lis r0, 0x0000 # bit 14 is reserved bit
ori r0, r0, 0x4000 # bit 31 is MSb
and r4, r4, r0 # clears all 0xa8 reg bits except reserved bits
;# lis r0, 0x3f75 #603 in drtry mode
lis r0, 0x3f37 #604 type processor
ori r0, r0, 0x0498 # LEAVE THE L2 CACHE OFF
;# ori r0, r0, 0x0698 # LEAVE THE L2 CACHE OFF but turn on dpark
or r4, r4, r0 # sets the desired bits
stwbrx r4, 0, r2 # write value to CONFIG_DATA