Chapter 5. Enhanced Multiply-Accumulate Unit (EMAC)
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Chapter 5
Enhanced Multiply-Accumulate
Unit
(EMAC)
This chapter describes the functionality, microarchitecture, and performance of the
enhanced multiply-accumulate (EMAC) unit in the ColdFire family of processors.
5.1 Multiply-Accumulate Unit
This document details the functionality, microarchitecture, and performance of the
hardware multiply-accumulate (MAC) unit in the ColdFire family of processors.
Motorola has incorporated a RISC-based processor design for peak performance and a
simplified version of the M68000 Family variable-length instruction set for maximum code
density. The result is a family of 32-bit microprocessors optimized for embedded
applications requiring high performance in a small core size.
The ColdFire performance road map defines a series of microarchitecture versions that
couple with improved process technology to offer increasing levels of performance.
The MAC design centers on the notion of providing a limited set of DSP operations
currently used in embedded code, while supporting the integer multiply instructions of the
baseline ColdFire architecture.
The MAC provides functionality in three related areas:
Signed and unsigned integer multiplies
Multiply-accumulate operations supporting signed and unsigned integer operands as
well as signed, fixed-point, fractional operands
Miscellaneous register operations
The ColdFire family supports two MAC implementations with different performance levels
and capabilities for differing silicon costs. The original MAC is a three-stage execution
pipeline, optimized for 16-bit operands and featuring a 16x16 multiply array with a single
32-bit accumulator. The enhanced MAC (EMAC) features a four-stage pipeline optimized
for 32-bit operands, with a fully pipelined 32x32 multiply array and four 48-bit
accumulators. Either can be attached to any version (V2, V3, or V4) ColdFire core as
dictated by application requirements.
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