
Chapter 2. Registers
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2-11
Supervisor Programming Model
it is included here because it must be implemented by the system designer. It is written with
a MOVEC instruction using the CPU address 0xC0F. (See the
ColdFire Family
Programmer’s Reference Manual
.) MBAR can be read or written through the debug
module as a read/write register, as described in Chapter 11, “Debug Support.” Only the
debug module can read MBAR.
The valid bit, MBAR[V], is cleared at system reset to prevent incorrect references before
MBAR is written; other MBAR bits are uninitialized at reset. To access internal peripherals,
write MBAR with the appropriate base address (BA) and set MBAR[V] after system reset.
All internal peripheral registers occupy a single relocatable memory block along 4-Kbyte
boundaries. If MBAR[V] is set, MBAR[BA] is compared to the upper 20 bits of the full
32-bit internal address to determine if an internal peripheral is being accessed. MBAR
masks specific address spaces using the address space fields. Attempts to access a masked
address space generate an external bus access.
Addresses hitting overlapping memory spaces take the following priority:
1. MBAR
2. RAM, ROM, and caches
3. Chip select
NOTE:
The MBAR region must be mapped to non-cacheable space.
Table 2-3 describes MBAR fields.
31
12 11
9
8
7
6
5
4
3
2
1
0
Field
BA
—
WP — AM C/I SC SD UC UD V
Reset
Undefined
0
R/W
W (supervisor only); R/W through debug module (only the debug module can read MBAR)
Rc
0x0C0F
Figure 2-9. Module Base Address Register (MBAR)
Table 2-3. MBAR Field Descriptions
Bits
Field
Description
31–12
BA
Base address. Defines the base address for a 4-Kbyte address range.
11–9
—
Reserved, should be cleared.
8
WP
Write protect. Mask bit for write cycles in the MBAR-mapped register address range.
0 Module address range is read/write.
1 Module address range is read only.
7
—
Reserved, should be cleared.
Attribute Mask Bits
F
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n
.