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ColdFire CF4e Core User’s Manual
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Cache Overview
Figure 8-21. Data Cache Line State Diagram—Copyback Mode
Figure 8-22 shows the two possible states for a cache line in write-through mode.
Figure 8-22. Data Cache Line State Diagram—Write-Through Mode
Table 8-31 describes data
cache line transitions and the accesses that cause them.
Table 8-31. Data Cache Line State Transitions
Access
Previous State
Invalid (V = 0)
Valid (V = 1, M = 0)
Modified (V = 1, M = 1)
Read
miss
CI1,
WI1
Read line from
memory and update
cache;
supply data to
processor;
go to valid state.
CV1,
WV1
Read new line from
memory and update
cache;
supply data to processor;
stay in valid state.
CD1
Push modified line to
buffer;
read new line from memory
and update cache;
supply data to processor;
write push buffer contents
to memory;
go to valid state.
Read hit
CI2,
WI2
Not possible.
CV2,
WV2
Supply data to processor;
stay in valid state.
CD2
Supply data to processor;
stay in modified state.
Invalid
V = 0
CD1—CPU
read miss
CI3—CPU
write miss
Valid
V = 1
M = 0
Modified
V = 1
M = 1
CI5—DCINVA
CI6—CPUSHL & DDPI
CI7—CPUSHL & DDPI
CV1—CPU read miss
CV2—CPU read hit
CV7—CPUSHL & DDPI
CD2—CPU read hit
CD3—CPU write miss
CD4—CPU write hit
CD5—DCINVA
CD6—CPUSHL & DDPI
CV3—CPU write miss
CV4—CPU write hit
CI1—CPU read miss
CV5—DCINVA
CV6—CPUSHL & DDPI
CD7—CPUSHL
& DDPI
WI1—CPU read miss
Invalid
V = 0
Valid
V = 1
WI3—CPU write miss
WI5—DCINVA
WI6—CPUSHL & DDPI
WI7—CPUSHL & DDPI
WV1—CPU read miss
WV2—CPU read hit
WV3—CPU write miss
WV4—CPU write hit
WV7—CPUSHL & DDPI
WV5—DCINVA
WV6—CPUSHL & DDPI
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