Chapter 4. Floating-Point Unit (FPU)
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4-13
FPU Programmer’s Model
example, the rounding precision for FADD is determined by FPCR, while the rounding
precision for FSADD is single-precision, independent of FPCR.
Range control helps emulate devices that support only single-precision arithmetic by
rounding the intermediate result’s mantissa to the specified precision and checking that the
intermediate exponent is in the representable range of the selected rounding precision. If
the intermediate result’s exponent exceeds the range, the appropriate underflow or
overflow value is stored as the result in the double-precision format exponent. For
example, if the data format and rounding mode is single-precision RM and the result of an
arithmetic operation overflows the single-precision format, the maximum normalized
single-precision value is stored as a double-precision number in the destination
floating-point data register; that is, the unbiased 11-bit exponent is 0x0FF and the 52-bit
fraction is 0xF_FFFF_E000_0000. If an infinity is the appropriate result for an underflow
or overflow, the infinity value for the destination data format is stored as the result; that is,
the exponent has the maximum value and the mantissa is zero.
Figure 4-12 shows the algorithm for rounding an intermediate result to the selected
rounding precision and destination data format. If the destination is a floating-point
register, the rounding boundary is determined by either the selected rounding precision
specified by FPCR[PREC] or by the instruction itself. For example, FSADD and FDADD
specify single- and double-precision rounding regardless of FPCR[PREC]. If the
destination is memory or an integer data register, the destination data format determines
the rounding boundary. If the rounded result of an operation is inexact, INEX is set in
FPSR[EXC].
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