INDEX
Index
Index-1
A
AATR, 11-26
ABLR/ABHR, 11-26
Address map
CPU, 1-7
Addressing
modes, 1-12
variant, 11-8
Architectural summary, 1-3
Architecture
virtual memory management, 10-1
B
BDM
address attribute register, 11-16
command
format, 11-33
sequence diagrams, 11-34
set descriptions, 11-35
command set summary, 11-32
extension words as required, 11-33
Motorola-recommended pinout, 11-68
receive packet format, 11-30
serial interface, 11-29
transmit packet format, 11-31
BIST
core ports, 12-19
general, 12-17
memory
clock determination, 12-27
controllers, 12-18
data retention, 12-26
modify ROM signature script, 12-23
power analysis, 12-20
ROM algorithm, 12-22
staging of memories, 12-20
test modes, 12-25
testing algorithms, 12-21
timing
cycles, 12-26
diagrams, 12-28
Branch instruction execution timing, 6-28
Buffers
cache push and store, 8-43
Bus
arbitration, 9-16
basic cycles, 9-8
controller system, 8-18
pipelined cycles, 9-9
C
Cache
accesses, 8-39
buffer bus operation, 8-43
caching modes, 8-38
coherency, 8-42
control register, 8-46
copyback mode, 8-39
data state transitions, 8-53
filling, 8-42
inhibited accesses, 8-39
instruction state transitions, 8-52
locking, 8-44
management, 8-50
memory accesses for maintenance, 8-42
operation
general, 8-35
summary, 8-52
optimizing recommendation, 8-33
organization, 8-33
overview, 8-32
protocol, 8-40
push and store buffers, 8-43
pushes, 8-42
read hit, 8-41
read miss, 8-41
registers, 8-45
registers, access control, 8-48
start-up, 8-34
write hit, 8-42
write miss, 8-41
write-through mode, 8-39
CCR, 2-5
CF4eTW architecture example, 12-7
ColdFire core status register, 2-8
ColdFire debug
Revision B, 11-66
Revision C, 11-67
Core
features, 1-1
implementation block diagram, 1-2
overview, 1-1
supervisor status register, 5-7
F
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