
INDEX
Index-2
ColdFire CF4e Core User’s Manual
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Core interface
address and data phase interactions, 9-10
basic bus cycles, 9-8
bus arbitration, 9-16
CF4e pin characteristics, 9-2
ColdFire master bus, 9-6
data size operations, 9-12
line transfers, 9-13
M-Bus operation, 9-8
M-Bus signals, 9-6
pipelined bus cycles, 9-9
signals, 9-1
timing characteristics, 13-1
CPU address map, 1-7
D
Data cache state transitions, 8-53
Data organization
registers, 1-9
Data representation
EMAC, 1-11
Debug
attribute trigger register, 11-13
background mode (BDM), 11-27
breakpoint operation theory, 11-55
C definition of PSTDDATA outputs, 11-58
ColdFire
history, 11-65
Revision C, 11-67
Coldfire
Revision B, 11-66
concurrent BDM and processor operation, 11-58
configuration/status register, 11-17
CPU halt, 11-28
data breakpoint/mask registers, 11-19
dump memory block, 11-41
emulator mode, 11-57
fill memory block, 11-43
force transfer acknowledge, 11-47
interrupts and requests (emulator mode), 11-67
no operation, 11-46
overview, 11-1
PC breakpoint ASID register, 11-26
program counter breakpoint/mask registers, 11-20
programming model
address attribute trigger register (AATR), 11-26
address
breakpoint
ABHR), 11-26
general, 11-10
trigger definition register (TDR), 11-23
read
A/D register, 11-36
control register, 11-49
memory location, 11-38
registers
(ABLR,
register, 11-53
real-time trace support, 11-55
general, 11-5
processor halted, 11-9
processor stopped, 11-9
registers
address attribute (AATR), 11-26
address breakpoint (ABLR, ABHR), 11-26
trigger definition (TDR), 11-24
resume execution, 11-45
Revision A shared resources, 11-13
signal descriptions
general, 11-3
processor status/debug data, 11-4
supervisor instruction set, 11-64
taken branch, 11-8
trigger definition register, 11-21
user instruction set, 11-59
write
control register, 11-52
memory location, 11-39
register, 11-54
writeA/D register, 11-37
Debugging in a virtual environment, 10-7
DSCLK, 11-3
E
EMAC
data representation, 1-11, 5-13
instruction
execution times, 6-28
set summary, 5-12
memory map/register set, 5-6
multiply-accumulate unit, 5-1
OEP sequence stalls, 6-13
programming model, 2-6
Exception processing
overview, 7-1
precise faults, 7-8
processor exceptions, 7-5
sack frame definition, 7-4
supervisor/user stack pointers, 7-3
Exceptions, processor, 7-5
Execution locations, instruction, 6-18
Execution times
branch instruction, 6-28
EMAC instruction, 6-28
FPU instruction, 6-30
instruction, 6-21
miscellaneous, 6-27
miscellaneous instruction, 6-27
MOVE instruction, 6-23
one-operand, 6-24
two-operand, 6-25
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