8-14
ColdFire CF4e Core User’s Manual
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Local Memory Connection Specification
Figure 8-7. Cache Organization and Line Format (32-Kbyte Cache Size Shown)
The controller uses the icsize[3:0] input to determine the connected array sizes, as shown
in Table 8-10.
The signals in Table 8-11 connect the instruction cache controller to its SRAM array.
Table 8-10. Instruction Cache Size
icsize[3:0]
Total Size Data Array
Configuration Data Array
Total Depth Tag Array
Configuration Tag Array
0000
0 bytes
Instruction cache disabled
0 rows
Instruction cache disabled
0001
0 bytes
Instruction cache disabled
0 rows
Instruction cache disabled
0010
0 bytes
Instruction cache disabled
0 rows
Instruction cache disabled
0011
2 Kbytes
4 x 128 X 4 bytes
32 rows
32 X 25 bits
0100
4 Kbytes
4 x 256 X 4 bytes
64 rows
64 X 24 bits
0101
8 Kbytes
4 x 512 X 4 bytes
128 rows
128 X 23 bits
0110
16 Kbytes
4 x 1024 X 4 bytes
256 rows
256 X 22 bits
0111
32 Kbytes
4 x 2048 X 4 bytes
512 rows
2512 X 21 bits
1000–1111
RFU
RFU
RFU
RFU
Table 8-11. Instruction Cache Memory Array Connections
Direction/Size
Signal Name
Bus Width
Definition
Output
nsientb
Next-state instruction cache tag enable
Output
nsiwrttb
Next-state instruction cache tag write
Output
nsiwlvt
[3:0]
Next-state instruction cache tag write level
Output
nsirowst
[9:0]
Next-state instruction cache tag address
Output
nsiaddrt
[31:9]
Next-state instruction cache tag data
Output
nsisw
Next-state instruction cache tag written bit
Level 0
Level 1
Level 2
Level 3
Line
Set 0
Set 1
Set 510
Set 511
TAG
V D
LW0
LW1
LW2
LW3
Where:
TAG—19-bit address tag
V—Valid bit for line
D—Dirty bit for line
LWn—Longword
n
(32-bit) data entry
Cache Line Format
F
Freescale Semiconductor, Inc.
n
.