
Chapter 8. Local Memory
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Cache Overview
8.7.6.1 Read Miss
A processor read that misses in the cache requests the cache controller to generate a bus
transaction. This bus transaction reads the needed line from memory and supplies the
required data to the processor core. The line is placed in the cache in the valid state.
8.7.6.2 Write Miss (Data Cache Only)
The cache controller handles processor writes that miss in the data cache differently for
write-through and copyback regions. Write misses to copyback regions cause the cache line
to be read from system memory, as shown in Figure 8-14.
Figure 8-14. Write-Miss in Copyback Mode
The new cache line is then updated with write data and the M bit is set for the line, leaving
it in modified state. Write misses to write-through regions write directly to memory without
loading the corresponding cache line into the cache.
8.7.6.3 Read Hit
On a read hit, the cache provides the data to the processor core and the cache line state
remains unchanged. If the cache mode changes for a specific region of address space, lines
in the cache corresponding to that region that contain modified data are not pushed out to
memory when a read hit occurs within that line. First execute a CPUSHL instruction or set
CACR[DCINVA,ICINVA] before switching the cache mode.
Cache Line
System
Memory
V = 1
M = 0
1. Writing character X to 0x0A generates a write miss. Data cannot be written to an invalid line.
V = 0
M = 0
0x0C
0x00
0x08
0x04
2. The cache line (characters A–P) is updated from system memory, and the line is marked valid.
X
ABCD EFGH IJKL MNOP
3. After the cache line is filled, the write that initiated the write miss (the character X) completes.
V = 1
M = 1
0x0C
ABCD EXGH IJKL MNOP
0x00
0x08
0x04
0x0C
0x00
0x08
0x04
Core
Core
F
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