
Chapter 11. Debug Support
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11-49
Background Debug Mode (BDM)
11.5.3.3.11 Read Control Register (
RCREG
)
Read the selected control register and return the 32-bit result. Accesses to the
processor/memory control registers are always 32 bits wide, regardless of register width.
The second and third words of the command form a 32-bit address, which the debug
module uses to generate a special bus cycle to access the specified control register. The
12-bit Rc field is the same as that used by the MOVEC instruction.
Command/Result Formats:
Rc encoding: See Table 2-4.
Command Sequence:
Figure 11-43.
RCREG
Command Sequence
Operand Data:
Result Data:
The only operand is the 32-bit Rc control register select field.
Control register contents are returned as a longword,
most-significant word first. The implemented portion of registers
smaller than 32 bits is guaranteed correct; other bits are undefined.
BDM Accesses of the Stack Pointer Registers (A7: SSP and USP)
The Version 4 ColdFire core supports two unique stack pointer (A7) registers: the
supervisor stack pointer (SSP) and the user stack pointer (USP). The hardware
implementation of these two programmable-visible 32-bit registers does not uniquely
identify one as the SSP and the other as the USP. Rather, the hardware uses one 32-bit
register as the currently-active A7; the other is named simply the OTHER_A7. Thus, the
contents of the two hardware registers is a function of the operating mode of the processor:
if SR[S] = 1
then
A7 = Supervisor Stack Pointer
OTHER_A7 = User Stack Pointer
15
12
11
8
7
4
3
0
Command
0x2
0x9
0x8
0x0
0x0
0x0
0x0
0x0
0x0
Rc
Result
D[31:16]
D[15:0]
Figure 11-42.
RCREG
Command/Result Formats
EXT WORD
"NOT READY"
EXT WORD
"NOT READY"
RCREG
NEXT CMD
"NOT READY"
XXX
"NOT READY"
XXX
XXX
BERR
MS RESULT
READ
REGISTER
NEXT CMD
LS RESULT
MS ADDR
CONTROL
MS ADDR
F
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