
Chapter 8. Local Memory
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8-5
Two-Stage Pipelined Local Bus (K-Bus)
Memory outputs are held valid until the next rising edge of the clock.
A generic port list and synchronous memory functionality are shown in Figure 8-5.
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Figure 8-5. Synchronous Memory Interface Block Diagram
In Figure 8-5, the memory address width is a function of the capacity of the local memory,
and the data bus widths (DBI and DBO) are a function of the type of synchronous memory
(cache, RAM, or ROM). The port names for the memory block are defined as follows: A is
the reference address, CSB is an active-low chip select, DBI is the data bus input, RWB is
the read/write control (read = 1, write = 0), CLK is the processor’s clock, and DBO is the
data bus output.
The corresponding functional truth table is shown in Table 8-1.
8.2 Two-Stage Pipelined Local Bus (K-Bus)
In the pipelined K-Bus design, consider a read operation. The first stage (KC1) is dedicated
to the actual memory access, while the second stage (KC2) supports data transmission back
to the processor. This structure provides an optimum time balance of the basic functions
associated with a K-Bus reference, because it effectively provides an entire machine cycle
for the memory array access.
The pipelined operation actually begins with a J cycle, where part of the reference address
and certain control signals are sent from the processor to the K-Bus memory controllers in
the cycle immediately preceding the KC1 stage. This transmission is necessary to allow
controllers/arrays to have a local registered copy of the time-critical portion of the reference
address.
Table 8-1. Synchronous Memory Truth Table (Sampled at Positive Edge of CLK)
CSB
RWB
Operation
1
x
Idle (minimum power)
0
1
Read memory, DBO = Memory[A]
0
0
Write memory, Memory[A] = DBI
A
CLK
DBI
CSB
DBO
Variable
Variable
Variable
RWB
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