
Chapter 12. Test
12-29
BIST
During address 0 when there is a minimum automatic hold, bistdata is [data, data,
data, data, data, data, data, data].
During address 0 when there is not an automatic hold, bistdata is [data, data, data,
data, data, data].
At all other addresses, bistdata is [data,data,data,DATA,DATA,data], in this case
[1,1,1,2,2,1].
The bistdata signals always operate at half the processor clock frequency. All other BIST
input and output pins are clocked by the system clock. In this example, the
system/processor clock ratio is 2:1, only the processor clock is displayed. This ratio can be
2:1, 3:1, or 4:1. This example is specific to EBIST tag arrays.
Figure 12-21. EBIST Timing Diagram for an 8-Kbyte Cache Tag Array
Figure 12-21 shows EBIST test 0 with background 0. The bistdata output for part of the
array is data 1, data 2 due to the fact that the tag arrays widths are maximum of 25 bits.
Figure 12-5 shows variations on the BIST data output for the difference size memory arrays
given the test number and background. The information in the table is data, data, and old
data, where old data is the data from the last background.
Table 12-5. EBIST Tag Output Data
Tag
Size
Test 0
Test 1
Test 2+
Bckgnd 0
Bckgnd 1
Bckgnd 2
Bckgnd 0
Bckgnd 1
Bckgnd 2
Bckgnd 0
Bckgnd 1
Bckgnd 2
2K
5, A, X
3, C, 5
0, F, 3
5, A, 0
3, C, 5
0, F, 3
5, A, 0
3, C, 5
0, F, 3
4K
1, A, X
3, 8, 1
0, D, 3
5, A, 0
3, C, 5
0, F, 3
5, A, 0
3, C, 5
0, F, 3
8K
1, 2, X
3, 0, 1
0, 3, 3
5, A, 0
3, C, 5
0, F, 3
5, A, 0
3, C, 5
0, F, 3
processor clk
mtmod[2:0]
bistmemory[2:0]
bistrelease
bistdone
bistfail
*memory datain[31:7]
*memory address[31:0]
bistdata[3:0]
bisthold
3096 3097 3098 3099 3100 3101 3102 3103 310431-053106 3107 3108 3109 3110 3111 3112 3113 3114 3115
*memory dataout[31:7]
110
010
127
0
1
155555D
0AAAAA2
1555551
0AAAAA2
1555551
1555551
x...x
2
1
1
* internal signals
0AAAAA2
F
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Go to: www.freescale.com
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