
INDEX
Index
Index-3
F
Fault-on-fault halt, 11-28
FPU
computational accuracy, 4-11
conditional testing, 4-16
control register, 4-8
data registers, 4-8
data types, 4-4
denormalized numbers, 4-5
infinities, 4-5
normalized numbers, 4-4
not-a-number, 4-5
zeros, 4-4
exceptions
arithmetic, 4-20
branch/set on unordered (BSUN), 4-21
divide-by-zero (DZ), 4-25
general, 4-19
inexact result (INEX), 4-25
input
denormalized number (IDE), 4-22
not-a-number (INAN), 4-22
operand error (OPERR), 4-23
overflow (OVFL), 4-23
state frames, 4-26
underflow (UNFL), 4-24
floating-point data formats, 4-3
instruction
address register, 4-11
execution times, 4-30, 6-30
instructions
overview, 4-28
notational conventions, 4-2
operand data formats and types, 4-3
overview, 4-1
post processing, 4-15
programmer’s model, 4-7
programming model, 2-6
differences, 4-31
results
intermediate, 4-11
rounding, 4-12
signed-integer data formats, 4-3
status register, 4-9
underflow, round, overflow, 4-16
FPU-specific OEP stalls, 6-14
H
Halt, fault-on-fault, 11-28
I
Instruction
execution locations, 6-18
execution times, 6-21, 6-27
Instruction cache state transitions, 8-52
Instruction set
fetch pipeline, 6-4
overview, 1-13
summary, 1-16
Integer data formats, memory, 1-10
K
K-Bus signal connections, 8-8
L
Limited superscalar OEP, 6-9
Local memory
connection specification, 8-8
interactions between modules, 8-7
K-Bus array signal connections, 8-8
overview, 8-1
SRAM overview, 8-22
two-stage pipelined local bus (K-Bus), 8-5
M
MAC
fractional operation mode, 5-9
general operation, 5-3
introduction, 5-2
mask register, 5-11
opcodes, 5-13
overview, 5-1
status register, 5-6
MBAR, 2-10
M-Bus
interrupt support, 9-18
reset operation, 9-18
MC680x0 differences, 4-31
Memory
accesses for cache maintenance, 8-42
integer data formats, 1-10
MMU
architecture
features, 10-2
location, 10-2
architecture implementation
access, 10-4
access error stack frame, 10-5
ACR address improvements, 10-6
changes to ACRs and CACR, 10-6
expanded control register space, 10-6
general, 10-3
instruction and data cache addresses, 10-4
precise faults, 10-4
supervisor protection, 10-7
F
Freescale Semiconductor, Inc.
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