Chapter 7. Exception Processing
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7-5
Processor Exceptions
7.4 Processor Exceptions
Table 7-3 describes CF4e exceptions. Note that if a ColdFire processor encounters any fault
while processing another fault, it immediately halts execution with a catastrophic
fault-on-fault condition. A reset is required to force the processor to exit this halted state.
Table 7-2. Format/Vector Word
Bits
Field
Description
31–28
FORMAT Format field. Written with a value of {4,5,6,7} by the processor indicating a 2-longword frame
format. FORMAT records any longword stack pointer misalignment when the exception occurred.
A7 at Time of Exception, Bits[1:0]
A7 at First Instruction of Handler
FORMAT
00
Original A7—8
0100
01
Original A7—9
0101
10
Original A7—10
0110
11
Original A7—11
0111
27–26
FS[3–2]
Fault status. Defined for access and address errors and for interrupted debug service routines.
0000 Not an access or address error nor an interrupted debug service routine
0001 Reserved
0010 Interrupt during a debug service routine for faults other than access errors.
1
0011 Reserved
0100 Error (for example, protection fault) on instruction fetch
0101 TLB miss on opword of instruction fetch (New in CF4e)
0110 TLB miss on extension word of instruction fetch (New in CF4e)
0111 IFP access error while executing in emulator mode (New in CF4e)
1000 Error on data write
1001 Error on attempted write to write-protected space
1010 TLB miss on data write (New in CF4e)
1011 Reserved
1100 Error on data read
1101 Attempted read, read-modify-write of protected space (New in CF4e)
1110 TLB miss on data read, or read-modify-write (New in CF4e)
1111 OEP access error while executing in emulator mode (New in CF4e)
1
This generally refers to taking an I/O interrupt during a debug service routine but also applies to other fault
types. If an access error occurs during a debug service routine, FS is set to 0111 if it is due to an instruction
fetch or to 1111 for a data access. This applies only to access errors with the MMU present. If an access error
occurs without an MMU, FS is set to 0010.
25–18
VEC
Vector number. Defines the exception type. It is calculated by the processor for internal faults and
is supplied by the peripheral for interrupts. See Table 7-1.
17–16
FS[1–0]
See bits 27–26.
F
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