
11-24
ColdFire CF4e Core User’s Manual
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Programming Model
A write to the XTDR clears the trigger status bits, CSR[BSTAT].
Section 11.4.9.1, “Resulting Set of Possible Trigger Combinations,” describes how to
handle multiple breakpoint conditions.
Table 11-19 describes XTDR fields.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17 16
Field
—
EBL
EDLW EDWL EDWU EDLL EDLM EDUM EDUU
DI
EAI
EAR
EAL
—
Reset
—
00_0000_0000_000
—
R/W
—
Write
—
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Field
—
EBL
EDLW EDWL EDWU EDLL EDLM EDUM EDUU
DI
EAI
EAR
EAL
—
Reset
—
00_0000_0000_000
—
R/W
—
Write
—
DRc[4–0]
0x17
Figure 11-14. Extended Trigger Definition Register (XTDR)
Table 11-19. XTDR Field Descriptions
Bits
Name
Description
29/13
EBL
Enable breakpoint level. If set, EBL is the global enable for the breakpoint trigger; that is, if
TDR[EBL] or XTDR[EBL] is set, a breakpoint trigger is enabled. Clearing both disables all
breakpoints.
28–22
12–6
ED
x
Setting an ED
x
bit enables the corresponding data breakpoint condition based on the size and
placement on the processor’s local data bus. Clearing all ED
x
bits
disables data breakpoints.
28/12
EDLW
Data longword. Entire processor’s local data bus.
27/11
EDWL
Lower data word.
26/10
EDWU
Upper data word.
25/9
EDLL
Lower lower data byte. Low-order byte of the low-order word.
24/8
EDLM
Lower middle data byte. High-order byte of the low-order word.
23/7
EDUM
Upper middle data byte. Low-order byte of the high-order word.
22/6
EDUU
Upper upper data byte. High-order byte of the high-order word.
21/5
DI
Data breakpoint invert. Provides a way to invert the logical sense of all the data breakpoint
comparators. This can develop a trigger based on the occurrence of a data value other than the
DBR1 contents.
Second-Level Triggers
First-Level Triggers
F
Freescale Semiconductor, Inc.
n
.