Chapter 10. Memory Management Unit (MMU)
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10-19
MMU Implementation
The optional MMU is referenced concurrently with the memory unit access controllers. It
has two independent control sections to simultaneously process an instruction and data
K-Bus request. Figure 10-1 shows how the MMU and memory unit access controllers fit in
the K-Bus pipeline. As the diagram shows, core address and attributes are used to access
the mapping registers and the MMU. By the middle of the KC1 cycle, the K-Bus physical
memory address (KADDR_KC1) is available along with its corresponding access control.
Figure 10-10 shows more details of the MMU structure. The TLB is accessed at the
beginning of the KC1 pipeline stage so the resulting physical address can be sourced to the
cache controllers to factor into the cache hit/miss determination. This is required because
caches are virtually indexed but physically mapped.
Figure 10-10. K-Bus Address and Attributes Generation
10.6 MMU Implementation
The MMU implements a 64-entry full-associative Harvard TLB architecture with 32-entry
ITLB and DTLB. This section provides more details of this specific TLB implementation.
This section details the operation and looks at the size, frequency, miss rate, and miss
recovery time of this specific TLB implementation.
JADDR, J Control
TLB Hit
KADDR_KC1
KC1 cycle access control
entries
Comp
TLB tag
entries
TLB data
entry
data
TLB hit
KC1
J
Memory unit access control
(MMUBAR, RAMBARs, ROMBARs,
ACRs, CACR priority hit logic)
Translated address
MMU’s access control
Untranslated address
mapping register’s
access control
Mapping register hit
or special mode access
To K-Bus memory controllers
plus K-to-M bus interface
To K-Bus memory controllers
To K-Bus control for
TLB miss logic
To K-Bus control for
TLB miss logic
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