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ColdFire CF4E Core User’s Manual
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ColdFire Master Bus
Figure 9-10. Line Access Write with One Wait State
9.3.2.6 Bus Arbitration
The arbitration block provides a multiplexed bus scheme to handle multiple M-Bus
masters. Multiple masters cannot be on the same physical bus. Figure 9-11 shows the top
level architecture of a two-master, multiplexed M-Bus system. The address, attributes,
write data, mapb, and mdpb are multiplexed to the SIM. The current bus master’s signals
are muxed onto the common bus. The termination and address hold signals are
demultiplexed and routed to the appropriate bus master. Reset signals and read data need
not be multiplexed. Arbitration logic generates address hold to stall a device that is not the
current bus master.
The multiplexing scheme was adopted to accommodate a standard cell methodology. There
are no three-state or bidirectional signals on the bus, so adding bus masters complicates
multiplexing and may affect timing. Designs should limit the number of M-Bus masters.
For instance, a three-channel DMA is preferable to three DMA modules on the M-Bus.
Figure 9-11. Multiplexed M-Bus Structure
Figure 9-11 shows waveforms with two bus masters multiplexed onto a common M-Bus.
The exact arbitration scheme and relative priority of bus masters is determined by the
maddr[31:0]
and attributes
mapb
mahb
mdpb
mtab
mrwb
mwdata
Clock
Bus Master
#1
Bus Master
#2
Bus Arbitration
And
Multiplexing
System
Bus
Controller
M-Bus #1
M-Bus #2
Common
M-Bus
External
Bus
S-Bus
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