11-10
ColdFire CF4e Core User’s Manual
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Programming Model
The B marker occurs on the most-significant nibble of PSTDDATA with the data of
0xFF following:
PSTDDATA[7:0]
0xBF
0xFF
0xFF
0xFF
0xFX (X indicates that the next PST value is guaranteed to not be 0xF.)
The B marker occurs on the least-significant nibble of PSTDDATA with the data of
0xFF following:
PSTDDATA[7:0]
0xYB
0xFF
0xFF
0xFF
0xFF
0xXY (X indicates the PST value is guaranteed not to be 0xF, and Y signifies a
PSTDDATA value that doesn’t affect the 0xFF count.)
NOTE:
As the result of the above, a count of at least nine or more
sequential single 0xF values or five or more sequential 0xFF
values indicates the HALT condition.
11.4 Programming Model
In addition to the existing BDM commands that provide access to the processor’s registers
and the memory subsystem, the debug module contains 19 registers to support the
required functionality. These registers are also accessible from the processor’s supervisor
programming model by executing the WDEBUG instruction (write only). Thus, the
breakpoint hardware in the debug module can be read or written by the external
development system using the debug serial interface
or written by the operating system
running on the processor core. Software is responsible for guaranteeing that accesses to
these resources are serialized and logically consistent. Hardware provides a locking
mechanism in the CSR to allow the external development system to disable any attempted
writes by the processor to the breakpoint registers (setting CSR[IPW]). BDM commands
must not be issued if the WDEBUG instruction is used to access debug module registers or
the resulting behavior is undefined.
These registers, shown in Figure 11-5, are treated as 32-bit quantities, regardless of the
number of implemented bits.
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