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ColdFire CF4e Core User’s Manual
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CONTENTS
Paragraph
Number
Title
Page
Number
6.3.7
6.4
6.5
6.5.1
6.5.2
6.5.3
6.5.4
6.5.5
6.5.6
6.5.7
V4 OEP Summary ........................................................................................ 6-16
Instruction Execution Locations....................................................................... 6-18
Instruction Execution Times............................................................................. 6-21
MOVE Instruction Execution Times............................................................ 6-23
Execution Timings—One-Operand Instructions.......................................... 6-24
Execution Timings—Two-Operand Instructions.......................................... 6-25
Miscellaneous Instruction Execution Times................................................. 6-27
Branch Instruction Execution Times ............................................................ 6-28
EMAC Instruction Execution Times ............................................................ 6-28
FPU Instruction Execution Times................................................................. 6-30
Chapter 7
Exception Processing
7.1
7.2
Overview............................................................................................................. 7-1
Supervisor/User Stack Pointers
(A7 and OTHER_A7) 7-3
Exception Stack Frame Definition...................................................................... 7-4
Processor Exceptions.......................................................................................... 7-5
Precise Faults...................................................................................................... 7-8
7.3
7.4
7.5
Chapter 8
Local Memory
8.1
8.2
8.3
8.4
8.4.1
8.4.1.1
8.4.1.2
8.4.1.3
8.4.1.4
8.5
8.5.1
8.5.2
8.5.2.1
8.5.3
8.5.4
8.5.5
8.6
8.6.1
Local Memory Overview.................................................................................... 8-1
Two-Stage Pipelined Local Bus (K-Bus) ........................................................... 8-5
Interactions between Local Memory Modules ................................................... 8-7
Local Memory Connection Specification........................................................... 8-8
K-Bus Memory Array Signal Connections..................................................... 8-8
KRAM Information................................................................................... 8-8
KROM Controller Information................................................................. 8-10
Instruction Cache Information................................................................. 8-12
Data Cache Information........................................................................... 8-17
SRAM Overview .............................................................................................. 8-22
SRAM Operation.......................................................................................... 8-23
SRAM Programming Model......................................................................... 8-23
SRAM Base Address Registers (RAMBAR0/RAMBAR1)..................... 8-23
SRAM Initialization...................................................................................... 8-25
SRAM Initialization Code............................................................................ 8-26
Programming RAMBARs for Power Management...................................... 8-27
ROM Overview................................................................................................. 8-28
ROM Operation ............................................................................................ 8-28
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