Chapter 11. Debug Support
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11-11
Programming Model
Figure 11-5. Debug Programming Model
The registers in Table 11-7 are accessed through the BDM port by BDM commands,
WDMREG
and
RDMREG
, described in Section 11.5.3.3, “Command Set Descriptions.”
These commands contain a 5-bit field, DRc, that specifies the register, as shown in
Table 11-6.
Table 11-6. BDM/Breakpoint Registers
DRc[4–0]
Register Name
Abbreviation
Initial State
Page
0x00
Configuration/status register
1
CSR
0x0020_0000
p. 11-17
0x01–0x05
Reserved
—
—
—
0x04
PC breakpoint ASID control
PBAC
—
p. 11-26
0x05
BDM address attribute register
BAAR
0x0000_0005
p. 11-16
ABLR1
ABHR1
AATR1
PC breakpoint 1 register
PC breakpoint 2 register
PC breakpoint 3 register
PC breakpoint mask register
PC breakpoint register
Data breakpoint register
Data breakpoint mask register
Data breakpoint 1 register
Data breakpoint mask 1 register
Trigger definition register
Extended trigger definition register
XTDR
Configuration/status register
BDM address attributes register
Note: Each debug register is accessed as a 32-bit register; shaded fields above are not used (don’t care).
All debug control registers are writable from the external development system or the CPU via the
WDEBUG instruction.
CSR is write-only from the programming model. It can be read from and written to through the BDM port.
CSR is accessible in supervisor mode as debug control register 0x00 using the WDEBUG instruction and
through the BDM port using the
RDMREG
and
WDMREG
commands.
Address attribute trigger register
Address low breakpoint register
Address high breakpoint register
Address 1 attribute trigger register
Address low breakpoint 1 register
Address high breakpoint 1 register
31
15
7
0
31
15
7
0
31
15
7
0
31
15
0
31
15
0
31
15
0
31
15
0
31
15
0
31
15
0
31
15
0
31
15
0
AATR
ABLR
ABHR
BAAR
CSR
DBR
DBMR
PBR
PBR1
PBR2
PBR3
PBMR
DBR1
DBMR1
TDR
F
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