
11-48
ColdFire CF4e Core User’s Manual
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Background Debug Mode (BDM)
be logically summed into the normal acknowledge logic located in the system integration
module (SIM) outside of the ColdFire core.
There are two scenarios of interest, one caused by a processor access and the other caused
by a BDM access. The following sequences identify the operations needed to break the
hung bus condition:
Bus hang caused by processor or external or internal alternate master:
— Assert the breakpoint input to force a processor core halt.
— If the bus hang was caused by a processor access, send in
FORCE
_
TA
commands
until the processor is halted, as signaled by PST = 0xF. Due to pipeline and
store buffer depths, many memory accesses may be queued up behind the
access causing the bus hang. Repeated
FORCE
_
TA
commands eventually allow
processing of all these pending accesses. As soon as the processor is halted, the
system reaches a quiescent, controllable state.
— If the hang was caused by another master, such as a DMA channel, the
processor can halt immediately. In this case as well, multiple assertions of the
FORCE
_
TA
command may be required to terminate the alternate master’s errant
access.
Bus hang caused by BDM access:
— It is assumed the processor is already halted at the time of the errant BDM
access. To resolve the hung bus, it is necessary to process four or more
FORCE
_
TA
commands because the BDM command may have initiated a cache
line access, which fetches 4 longwords, each needing a unique transfer
acknowledge.
Formats:
Command Sequence:
Figure 11-41.
FORCE
_TA Command Sequence
Operand Data:
Result Data:
None
The command complete response, 0xFFFF (with the status bit
cleared), is returned during the next shift operation. This response
indicates the
FORCE
_
TA
command was processed correctly and does
not necessarily reflect the status of any internal bus.
15
12
11
8
7
4
3
0
0x0
0x0
0x0
0x2
Figure 11-40.
FORCE
_
TA
Command
FORCE_TA
NEXT CMD
“CMD COMPLETE”
F
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n
.