
8-34
ColdFire CF4e Core User’s Manual
For More Information On This Product,
Go to: www.freescale.com
Cache Overview
Figure 8-11. Data Cache Organization and Line Format
A set is a group of four lines (one from each level, or way), corresponding to the same index
into the cache array.
8.7.2.1 Cache Line States: Invalid, Valid-Unmodified, and
Valid-Modified
As shown in Table 8-27, a data cache line can be invalid, valid-unmodified (often called
exclusive), or valid-modified. An instruction cache line can be valid or invalid.
A valid line can be explicitly invalidated by executing a CPUSHL instruction
.
8.7.2.2 Cache at Start-Up
As Figure 8-12 (A) shows, after power-up, cache contents are undefined; V and M may be
set on some lines even though the cache may not contain the appropriate data for start-up.
Because reset and power-up do not invalidate cache lines automatically, the cache must be
cleared explicitly by setting CACR[DCINVA,ICINVA] before the cache is enabled (B).
After the entire cache is automatically flushed, cacheable entries are loaded first in way 0.
If way 0 is occupied, the cacheable entry is loaded into the same set in way 1, as shown in
Figure 8-12 (D). This process is described in detail in Section 8.7.3, “Cache Operation.”
Table 8-27. Valid and Modified Bit Settings
V
M
Description
0
x
Invalid. Invalid lines are ignored during lookups.
1
0
Valid, unmodified. Cache line has valid data that matches system memory.
1
1
Valid, modified. Cache line contains most recent data, data at system memory location is stale.
Way 0
Way 1
Way 2
Way 3
Line
Set 0
Set 1
Set n-1
Set n
TAG
V
M
Longword 0
Longword 1
Longword 2
Longword 3
Where:
TAG—21-bit address tag
V—Valid bit for line
M—Modified bit for line (data cache only)
Cache Line Format
F
Freescale Semiconductor, Inc.
n
.