Chapter 10. Memory Management Unit (MMU)
For More Information On This Product,
Go to: www.freescale.com
10-11
MMU Definition
providing access attributes. Each TLB entry maps a virtual page. Several page sizes are
supported. Features such as clear all and probe for hit help maintain TLBs.
Fault-free, virtual address accesses that hit in the TLB incur no pipeline delay. Accesses that
miss the TLB or hit the TLB but violate an access attribute generate an access error
exception. On an access error, software can reference address and information registers in
the MMU to retrieve data. Depending on the fault source, software can obtain and load a
new TLB entry, modify the attributes of an existing entry, or abort the faulting process.
10.5.3 MMU Organization
Access to the MMU memory-mapped region is controlled by MMUBAR, a 32-bit
supervisor control register at 0x008 that is accessed using MOVEC or the serial BDM
debug port. The
PRM
describes the MOVEC instruction.
10.5.3.1 MMU Base Address Register (MMUBAR)
Figure 10-3 shows MMUBAR. The default reset state is an invalid MMUBAR, so that the
MMU is disabled and the memory-mapped space is not visible.
Table 10-3 describes MMU base address register fields.
10.5.3.2 MMU Memory Map
MMUBAR holds the base address for the 64-Kbyte MMU memory map, shown in
Table 10-4. The MMU memory map area is not visible unless the MMUBAR is valid and
must be referenced aligned. A large portion of the map is reserved for future use.
31
16 15
1
0
Field
BA
—
V
Reset
—
0
R/W
R/W
Rc
0x008
Figure 10-3. MMU Base Address Register
Table 10-3. MMU Base Address Register Field Descriptions
Bits
Name
Description
31–16
BA
Base address. Defines the base address for the 64-Kbyte address space mapped to the MMU.
15–1
—
Reserved, should be cleared. Writes are ignored and reads return zeros.
0
V
Valid. Indicates when MMUMBAR contents are valid. BA is not used unless V is set.
0 MMUBAR contents are not valid.
1 MMUBAR contents are valid.
F
Freescale Semiconductor, Inc.
n
.