
12-28
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BIST
12.3.10 Timing Diagrams
Initialization is similar for PBIST and EBIST. In the PBIST mode example in Figure 12-20,
Only the first 27 cycles are shown; the remaining cycles should remain at the state shown
in cycle 27 unless there is a failure with the exception of bisthold and bistrelease. The
mtmod[2:0] signals are always assumed to be in non-BIST state before going into BIST
mode in cycle 3. In PBIST mode, core initialization takes 16 processor clocks, during
which the internal BIST control resets the internal control logic and toggles the BIST
outputs
bistdone
,
bistfail
, and
bisthold
for stuck-at-fault coverage.
The testing algorithm begins at cycle 30. For PBIST tests, bistfail and bistdone are
monitored. For EBIST tests, reinitialization between BIST runs takes 12 cycles and would
be represented by cycles 18–30.
Figure 12-20. PBIST Initialization
In Figure 12-21, an 8-Kbyte ICU tag array is tested with EBIST mode. The cycles shown
represent a transition from the [W(5)] March C+ part to the [R(5),W(A),R(A)] part. This
example shows bistdata output during address 0, [R(5)] March C+ part output data, all other
March C+ part output data, and a minimum data retention hold.
The first March Part [W(5)] bistdata is always data, or 5 in this case. Consider the following
cases:
Clocks/complete PBIST test
221184 +
X
4
×
221184 =
884736 +
X
110592 +
X
4
×
110592 =
442368 +
X
55296 +
X
4
×
55296=
221184 +
X
Clocks/complete EBIST test
Table 12-4. BIST Cycles
Parameter
Data Array (8K)
RAM Array (4K)
Tag Array (8K)
processor clk
mtmod[2:0]
bistmemory[2:0]
bistrelease
bistdone
bistfail
bistdata[3:0]
bisthold
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
27
100
101
F
Freescale Semiconductor, Inc.
n
.