
Chapter 11. Debug Support
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11-35
Background Debug Mode (BDM)
NOTE:
A not-ready response can be ignored except during a
memory-referencing cycle. Otherwise, the debug module can
accept a new serial transfer after 32 processor clock periods.
In cycle 3, the development system supplies the low-order 16 address bits. The
debug module always returns a not-ready response.
At the completion of cycle 3, the debug module initiates a memory read operation.
Any serial transfers that begin during a memory access return a not-ready response.
Results are returned in the two serial transfer cycles after the memory access
completes. For any command performing a byte-sized memory read operation, the
upper 8 bits of the response data are undefined and the referenced data is returned
in the lower 8 bits. The next command’s opcode is sent to the debug module during
the final transfer. If a memory or register access is terminated with a bus error, the
error status (S = 1, DATA = 0x0001) is returned instead of result data.
11.5.3.3 Command Set Descriptions
The following sections describe the commands summarized in Table 11-24.
NOTE:
The BDM status bit (S) is 0 for normally completed
commands; S = 1 for illegal commands, not-ready responses,
and transfers with bus-errors. Section 11.5.2, “BDM Serial
Interface,” describes the receive packet format.
Motorola reserves unassigned command opcodes for future expansion. Unused command
formats in any revision level perform a
NOP
and return an illegal command response.
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