9-4
ColdFire CF4E Core User’s Manual
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CF4e Pin Characteristics
57
Output
krom1csb
—
Next-state KROM 1 chip select
58
Output
krom1addr
[15:2]
Next-state KROM 1 address
59
Output
pstddata
[7:0]
Processor status and debug data
60
Output
dsdo
—
Development system data output
M-Bus Inputs
61
Input
mrdata
2
[31:0]
M-Bus read data
62
Input
mtab
3
—
M-Bus transfer acknowledge
63
Input
mahb
3
—
M-Bus address hold
64
Input
miplb
4
[2:0]
M-Bus interrupt request priority level
Miscellaneous Control and Debug Inputs
65
Input
mrstib
4
—
M-Bus reset
66
Input
dsclk
5
—
Development system clock
67
Input
dsdi
5
—
Development system data input
68
Input
mbkptb
5
—
Development system breakpoint
Test and Cache Configuration Inputs
69
Input
mtmod
[2:0]
Test mode indicators
70
Input
bistrelease
—
BIST release data retention
71
Input
bistmemory
[2:0]
BIST memory select
72
Input
si
[31:0]
Core parallel scan inputs
73
Input
se
—
Core parallel scan enable
74
Input
tbsi
[3:0]
Test boundary scan inputs
75
Input
tbsei
—
Test boundary scan enable—inputs
76
Input
tbseo
—
Test boundary scan enable—outputs
77
Input
tbte
—
Test boundary pcell test enable
78
Input
icsize
[3:0]
Encoded I-cache size
79
Input
ocsize
[3:0]
Encoded D-cache size
Inputs from K-Bus Memories + Memory Configuration Definitions
80
Input
ictag3do
[31:9]
I-cache level 3 tag data output
81
Input
icw3do
—
I-cache level 3 written bit output
82
Input
icv3do
—
I-cache level 3 valid bit output
83
Input
ictag2do
[31:9]
I-cache level 2 tag data output
84
Input
icw2do
—
I-cache level 2 written bit output
85
Input
icv2do
—
I-cache level 2 valid bit output
86
Input
ictag1do
[31:9]
I-cache level 1 tag data output
87
Input
icw1do
—
I-cache level 1 written bit output
Table 9-1. CF4e Pin Characteristics (Continued)
No.
Type
Name
Bus Width
1
Description
F
Freescale Semiconductor, Inc.
n
.