
8-16
ColdFire CF4e Core User’s Manual
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Local Memory Connection Specification
The tag array has one entry for every four entries in the data array. Therefore, the tag array
does not use ichadd[3:2]. The array address is connected as shown in Table 8-13 for all
supported instruction cache tag array sizes.
The instruction cache controller provides enough tag array write data bits for the smallest
supported cache size. Each larger cache size needs one fewer (low order) tag bit.
Unnecessary tag bits may be implemented in the tag array (the cache controller always
writes and reads them as 0) or they may be tied to 0 at the core boundary. The tag array write
data is connected as shown in Table 8-14 for all supported cache tag array sizes.
Table 8-12. Instruction Cache Data Array Address Connection
icsize[3:0]
Total Size
Configuration
Array Address
Unused Address
0000
0 bytes
Instruction cache disabled
—
nsirowsd[11:0]
0001
0 bytes
Instruction cache disabled
—
nsirowsd[11:0]
0010
0 bytes
Instruction cache disabled
—
nsirowsd[11:0]
0011
2 Kbytes
4 x 128 X 4 bytes
nsirowsd[6:0]
nsirowsd[11:7]
0100
4 Kbytes
4 x 256 X 4 bytes
nsirowsd[7:0]
nsirowsd[11:8]
0101
8 Kbytes
4 x 512 X 4 bytes
nsirowsd[8:0]
nsirowsd[11:9]
0110
16 Kbytes
4 x 512 X 4 bytes
nsirowsd[9:0]
nsirowsd[11:10]
0111
32 Kbytes
4 x 1024 X 4 bytes
nsirowsd[10:0]
nsirowsd[11]
1000–1111
RFU
RFU
RFU
RFU
Table 8-13. Instruction Cache Tag Array Address Connection
icsize[3:0]
Total Size
Configuration
Array Address
Unused Address
0000
0 rows
Instruction cache disabled
—
nsirowst[9:0]
0001
0 rows
Instruction cache disabled
—
nsirowst[9:0]
0010
0 rows
Instruction cache disabled
—
nsirowst[9:0]
0011
32 rows
32 X 25 bits
nsirowst[4:0]
nsirowst[9:5]
0100
256 rows
256 X 24 bits
nsirowst[5:0]
nsirowst[9:6]
0101
512 rows
512 X 23 bits
nsirowst[6:0]
nsirowst[9:7]
0110
1024 rows
1024 X 22 bits
nsirowst[7:0]
nsirowst[9:8]
0111
2048 rows
2048 X 21 bits
nsirowst[8:0]
nsirowst[9]
1000–1111
RFU
RFU
RFU
RFU
Table 8-14. Instruction Cache Tag Array Write Data Connection
icsize[3:0]
Total Size
Configuration
Array Write Data
Unused Write Data (Must Be Tied to 0)
0000
0 rows
Instruction cache disabled
—
nsiaddrt[31:9]:
nsisw:nsisv
0001
0 rows
Instruction cache disabled
—
nsiaddrt[31:9]
nsisw:nsisv
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