
INDEX
Index-4
ColdFire CF4e Core User’s Manual
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supervisor/user stack pointers, 10-5
virtual memory references, 10-4
virtual mode, 10-4
features, 10-1
instructions, 10-22
MMU definition
base address register, 10-11
control register, 10-12
effective address attribute determination, 10-9
fault, test, or TLB address register, 10-15
functionality, 10-10
general, 10-9
memory map, 10-11
operation, 10-18
operation register, 10-13
organization, 10-11
read/write tag and data entry registers, 10-15
status register, 10-14
TLB, 10-17
MMU implementation
general, 10-19
TLB address fields, 10-20
TLB locked entries, 10-21
TLB replacement algorithm, 10-20
MOVE
instruction
timing, 6-23
MOVEC instruction, 11-49
O
OEP
EMAC-specific sequence stalls, 6-13
general, 6-6
instruction folding, 6-9
sequence-related stalls, 6-11, 6-14
V4 conceptual model, 6-6
Operand memory sequence-related stalls, 6-16
P
Pinout, Motorola-recommended BDM, 11-68
Pipelines
instruction fetch, 6-4
operand execution, 6-6
PULSE instruction, 11-7
R
Registers
AATR, 11-13, 11-26
ABLR/ABHR, 11-15
access control (ACR0–ACR3), 2-10
address (A6–A0), 2-4
BAAR, 11-16
BDM address attribute, 11-16
cache, 8-45
cache access control, 8-48
cache control (CACR), 2-10, 8-46
condition code (CCR), 2-5
CSR, 11-17
data (D7–D0), 2-4
data breakpoint/mask, 11-19
data organization, 1-9
debug
ABLR/ABHR, 11-26
attribute trigger, 11-13
configuration/status, 11-17
PC breakpoint AISD, 11-26
TDR module, 11-24
F-P
control, 4-8
instruction address, 4-11
status, 4-9
MAC
mask, 5-11
status, 5-6
MASK, 2-5
MBAR, 2-10
MMU
base address, 10-11
control, 10-12
fault, test, or TLB address, 10-15
operation, 10-13
read/write tag and data entry, 10-15
PBR, 11-20
program counter, 2-5
programming model table, 2-12
RAM base address (RAMBAR0/RAMBAR1), 2-10
RAREG/RDREG, 11-36
RCREG, 11-49
RDMREG, 11-53
read
A/D, 11-36
control, 11-49
read debug module, 11-53
ROM base address, 8-29
ROM base address (ROMBAR0/ROMBAR1), 2-10
SIM, base address, 2-10
SR, 2-8
status, 2-8, 2-8
TDR, 11-21
trigger definition, 11-21
user programming model, 2-3
user stack pointer, 2-5
VB, 2-9
vector base, 2-9, 2-9, 7-2
WAREG/WDREG, 11-37
WCREG, 11-52
F
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n
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