Chapter 10. Memory Management Unit (MMU)
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10-9
MMU Definition
10.5 MMU Definition
The ColdFire MMU provides a virtual address, demand-paged memory architecture. The
MMU supports hardware address translation acceleration using software-managed TLBs.
It enforces permission checking on a per-memory request basis, and has control, status, and
fault registers for MMU operation.
10.5.1 Effective Address Attribute Determination
The ColdFire core generates an effective memory address for all instruction fetches and
data read and write memory accesses. The previous ColdFire memory access control model
is based strictly on physical addresses. Every memory request address is a physical address
that is analyzed by this logic and assigned address attributes, which include the following:
Cache mode
K-Bus RAM (KRAM) enable information
K-Bus ROM (KROM) enable information
Write protect information
Write mode information
These attributes control processing of the memory request. The address itself is not affected
by memory access control logic.
Instruction and data references base effective address attributes and access mode on the
instruction type and the effective address. K-Bus accesses are of the following two types:
0100
Error (for example, protection fault) on instruction fetch
0101
TLB miss on opword of instruction fetch (New in CF4e)
0110
TLB miss on extension word of instruction fetch (New in CF4e)
0111
IFP access error while executing in emulator mode (New in CF4e)
1000
Error on data write
1001
Attempted write of protected space
1010
TLB miss on data write (New in CF4e)
1011
Reserved
1100
Error on data read
1101
Attempted read, read-modify-write of protected space (New in CF4e)
1110
TLB miss on data read, or read-modify-write (New in CF4e)
1111
OEP access error while executing in emulator mode (New in CF4e)
Table 10-2. Fault Status Encodings (Continued)
FS
Definition
F
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n
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