
Chapter 8. Local Memory
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8-19
Local Memory Connection Specification
Figure 8-8. Cache Organization and Line Format (32 Kbyte Cache Size shown)
The controller uses ocsize[2:0] to determine the connected array sizes as shown in
Table 8-16.
The signals in Table 8-17 connect the data cache controller to its SRAM array:
Table 8-16. Data Cache Size
ocsize[3:0]
Total Size Data Array
Configuration Data Array
Total Depth Tag Array
Configuration Tag Array
0000
0 bytes
Data cache disabled
0 rows
Data cache disabled
0001
0 bytes
Data cache disabled
0 rows
Data cache disabled
0010
0 bytes
Data cache disabled
0 rows
Data cache disabled
0011
2 Kbytes
4 x 128 X 4 bytes
32 rows
32 X 24 bits
0100
4 Kbytes
4 x 256 X 4 bytes
64 rows
64 X 24 bits
0101
8 Kbytes
4 x 512 X 4 bytes
128 rows
128 X 24 bits
0110
16 Kbytes
4 x 1024 X 4 bytes
256 rows
256 X 24 bits
0111
32 Kbytes
4 x 2048 X 4 bytes
512 rows
2512 X 24 bits
1000–1111
RFU
RFU
RFU
RFU
Table 8-17. Data Cache Memory Array Connections
Direction/Size
Signal Name
Bus Width
Definition
Output
nsoentb
Next-state O-Cache tag enable
Output
nsowrttb
Next-state O-Cache tag write
Output
nsowlvt
[3:0]
Next-state O-Cache tag write level
Output
nsorowst
[9:0]
Next-state O-Cache tag address
Output
nsoaddrt
[31:9]
Next-state O-Cache tag data
Output
nsosw
Next-state O-Cache tag written bit
Level 0
Level 1
Level 2
Level 3
Line
Set 0
Set 1
Set 510
Set 511
TAG
V D
LW0
LW1
LW2
LW3
Where:
TAG—19-bit address tag
V—Valid bit for line
D—Dirty bit for line
LWn—Longword n (32-bit) data entry
Cache Line Format
F
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n
.