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ColdFire CF4e Core User’s Manual
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Cache Overview
8.7.6.4 Write Hit (Data Cache Only)
The cache controller handles processor writes that hit in the data cache differently for
write-through and copyback regions. For write hits to a write-through region, portions of
cache lines corresponding to the size of the access are updated with the data. The data is
also written to external memory. The cache line state is unchanged. For copyback accesses,
the cache controller updates the cache line and sets the M bit for the line. An external write
is not performed and the cache line state changes to (or remains in) the modified state.
8.7.7 Cache Coherency (Data Cache Only)
The CF4e provides limited cache coherency support in multiple-master environments. Both
write-through and copyback memory update techniques are supported to maintain
coherency between the cache and memory.
The cache does not support snooping (that is, cache coherency is not supported while
external or DMA masters are using the bus). Therefore, any on-chip DMAs access local
memory and do not maintain coherency with the data cache. Therefore, cache coherency is
left to the user.
8.7.8 Memory Accesses for Cache Maintenance
The cache controller performs all maintenance activities that supply data from the cache to
the core, including requests to the SIM for reading new cache lines and writing modified
lines to memory. The following sections describe memory accesses resulting from cache
fill and push operations.
8.7.8.1 Cache Filling
When a new cache line is required, the core system bus controller performs a burst-read
transfer on the system bus.
SIM line accesses implicitly request burst-mode operations from memory.
The first cycle of a cache-line read loads the longword entry corresponding to the requested
address. Subsequent transfers load the remaining longword entries.
A burst operation is aborted by a write-protection fault, which is the only possible access
error. Exception processing proceeds immediately. Note that unlike Version 2 and Version 3
access errors, in this version, the program counter stored on the exception stack frame
points to the faulting instruction. See Chapter 7, “Exception Processing.”
8.7.8.2 Cache Pushes
Cache pushes occur for line replacement and as required for the execution of the CPUSHL
instruction. To reduce the requested data’s latency in the new line, the modified line being
replaced is temporarily placed in the push buffer while the new line is fetched from
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