Chapter 1. Introduction
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1-7
Address Map
1.6 Address Map
Table 1-1 shows the ColdFire CPU space assignment reserved for program-visible
registers. In general, these registers can be read and written through this space for debug
accesses, initiated by an external emulator through the serial BDM communication
channel. All control and configuration registers can be written to using the privileged move
control register (MOVEC) instruction.
NOTE:
A core may not implement all registers or register fields defined
by the architecture, and it may implement additional registers
or fields.
Table 1-1 lists register names, the CPU space assignment, whether the register is written
from the processor using the MOVEC instruction, and the complete register name.
Table 1-1. ColdFire CPU Space Assignments
Name
CPU Space
Assignment
Written with MOVEC
Register Name
Memory Management Control Registers
CACR
0x002
Yes
Cache control register
ASID
0x003
Yes
Address space identifier
ACR0–ACR3
0x004–0x007
Yes
Access control registers [0:3]
MMUBAR
0x008
Yes
MMU base address register
Processor General-Purpose Registers
D0–D7
0x(0,1)80–0x(0,1)87
No
Data registers 0–7 (0 = load, 1 = store)
A0–A7
0x(0,1)88–0x(0,1)8F
No
Address registers 0–7 (0 = load, 1 = store)
A7 is user stack pointer
Processor Miscellaneous Registers
OTHER_A7
0x800
No
Other stack pointer
VBR
0x801
No
Vector base register
MACSR
0x804
No
MAC status register
MASK
0x805
No
MAC address mask register
ACC
0x806
No
MAC accumulator
ACC0–ACC3
0x806–0x80B
No
MAC accumulators 0–3
ACCEXT01
0x807
No
MAC accumulator 0, 1 extension bytes
ACCEXT23
0x808
No
MAC accumulator 2, 3 extension bytes
SR
0x80E
No
Status register
PC
0x80F
No
Program counter
Processor Floating-Point Registers
FPU0
0x810
No
32 msbs of floating-point data register 0
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