
Chapter 8. Local Memory
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8-55
Cache Overview
The following tables present the same information as Table 8-31, organized by the previous
state of the cache line. In Table 8-32 the previous state is invalid.
Write
miss
(copy-
back)
CI3
Read line from
memory and update
cache;
write data to cache;
go to modified state.
CV3
Read new line from
memory and update
cache;
write data to cache;
go to modified state.
CD3
Push modified line to
buffer;
read new line from memory
and update cache;
write push buffer contents
to memory;
stay in modified state.
Write
miss
(write-
through)
WI3
Write data to
memory;
stay in invalid state.
WV3
Write data to memory;
stay in valid state.
WD3 Write data to memory;
stay in modified state.
Cache mode changed for
the region corresponding to
this line. To avoid this state,
execute a CPUSHL
instruction or set
CACR[DCINVA,ICINVA]
before switching modes.
Write hit
(copy-
back)
CI4
Not possible.
CV4
Write data to cache;
go to modified state.
CD4
Write data to cache;
stay in modified state.
Write hit
(write-
through)
WI4
Not possible.
WV4
Write data to memory and
to cache;
stay in valid state.
WD4 Write data to memory and
to cache;
go to valid state.
Cache mode changed for
the region corresponding to
this line. To avoid this state,
execute a CPUSHL
instruction or set
CACR[DCINVA,ICINVA]
before switching modes.
Cache
invalidate
CI5,
WI5
No action;
stay in invalid state.
CV5,
WV5
No action;
go to invalid state.
CD5
No action (modified data
lost);
go to invalid state.
Cache
push
CI6,
CI7,
WI6,
WI7
No action;
stay in invalid state.
CV6,
WV6
No action; (DDPI = 0))
go to invalid state.
CD6
Push modified line to
memory; (DDPI = 0)
go to invalid state.
CV7,
WV7
No action; (DDPI = 1)
stay in valid state.
CD7
Push modified line to
memory; (DDPI = 1)
go to valid state.
Table 8-31. Data Cache Line State Transitions (Continued)
Access
Previous State
Invalid (V = 0)
Valid (V = 1, M = 0)
Modified (V = 1, M = 1)
F
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