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ColdFire CF4e Core User’s Manual
For More Information On This Product,
Go to: www.freescale.com
TABLES
Table
Number
Title
Page
Number
4-27
4-28
4-29
5-1
5-2
5-3
6-1
6-2
6-3
6-4
6-5
6-6
6-7
6-8
6-9
6-10
6-11
6-12
6-13
6-14
6-15
6-16
7-1
7-2
7-3
7-4
8-1
8-2
8-3
8-4
8-5
8-6
8-7
8-8
8-9
8-10
8-11
8-12
8-13
8-14
8-15
8-16
8-17
68K/ColdFire Operation Sequence 1..........................................................................4-32
68K/ColdFire Operation Sequence 2..........................................................................4-32
68K/ColdFire Operation Sequence 3..........................................................................4-32
MACSR Field Descriptions..........................................................................................5-7
Summary of S/U, F/I, and R/T Control Bits.................................................................5-9
EMAC Instruction Summary......................................................................................5-12
CFxCore Processor Execution Latency........................................................................6-2
V4 RTS Execution Times.............................................................................................6-5
Instructions that Make Results Available to Subsequent Instructions........................6-12
FPU Execution Example.............................................................................................6-15
V4 ColdFire Compute Engine Location.....................................................................6-18
Misaligned Operand References.................................................................................6-22
Move Byte and Word Execution Times......................................................................6-23
Move Long Execution Times......................................................................................6-23
MAC and Miscellaneous Move Execution Times......................................................6-24
One-Operand Instruction Execution Times................................................................6-25
Two-Operand Instruction Execution Times................................................................6-25
Miscellaneous Instruction Execution Times...............................................................6-27
General Branch Instruction Execution Times.............................................................6-28
Bcc Instruction Execution Times................................................................................6-28
EMAC Instruction Execution Times ..........................................................................6-29
FPU Instruction Execution Times, .............................................................................6-30
Exception Vector Assignments.....................................................................................7-2
Format/Vector Word.....................................................................................................7-5
Exceptions.....................................................................................................................7-6
OEP EX Cycle Operations............................................................................................7-8
Synchronous Memory Truth Table (Sampled at Positive Edge of CLK).....................8-5
KRAM Size...................................................................................................................8-9
KRAM Memory Array Connections ............................................................................8-9
KRAM0/KRAM1 Array Address Connection............................................................8-10
KRAM0/KRAM1 Byte Write Enables.......................................................................8-10
KRAM0/KRAM1 Size ...............................................................................................8-11
KROM{0,1} Memory Array Connections..................................................................8-11
KROM Array Address Connection.............................................................................8-12
Instruction Cache Sizes and Configurations...............................................................8-13
Instruction Cache Size................................................................................................8-14
Instruction Cache Memory Array Connections..........................................................8-14
Instruction Cache Data Array Address Connection....................................................8-16
Instruction Cache Tag Array Address Connection.....................................................8-16
Instruction Cache Tag Array Write Data Connection.................................................8-16
Data Cache Sizes and Configurations.........................................................................8-18
Data Cache Size..........................................................................................................8-19
Data Cache Memory Array Connections....................................................................8-19
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