7-4
ColdFire CF4E Core User’s Guide
For More Information On This Product,
Go to: www.freescale.com
Exception Stack Frame Definition
32-bit register as the currently-active A7 and the other as OTHER_A7. Thus, the register
contents are a function of the processor operating mode:
if SR[S] = 1
then
A7 = Supervisor Stack Pointer
other_A7 = User Stack Pointer
A7 = User Stack Pointer
other_A7 = Supervisor Stack Pointer
The BDM programming model supports reads and writes to A7 and OTHER_A7 directly.
It is the responsibility of the external development system to determine the mapping of (A7
and OTHER_A7) to the two program-visible definitions (SSP and USP), based on the
setting of SR[S]. This functionality is enabled by setting by the dual stack pointer enable
bit CACR[DSPE]. If this bit is cleared, only the stack pointer, A7 (defined for previous
ColdFire versions), is available. DSPE is zero at reset.
else
If DSPE is set, the appropriate stack pointer register (SSP or USP) is accessed as a function
of the processor’s operating mode. To support dual stack pointers, the following two
privileged MC680x0 instructions to load/store the USP are added to the ColdFire
instruction set architecture:
mov.l Ay,USP # move to USP: opcode = 0x4E6(0xxx)
mov.l USP,Ax # move from USP: opcode = 0x4E6(1xxx)
The address register number is encoded in the low-order 3 bits of the opcode.
7.3 Exception Stack Frame Definition
The first longword of the exception stack frame, Figure 7-1, holds the 16-bit format/vector
word (F/V) and 16-bit status register. The second holds the 32-bit program counter address.
Figure 7-1. Exception Stack Frame
Table 7-2 describes F/V fields. FS encodings added to support the CF4e MMU are noted.
31
28
27
26
25
18
17
16
15
0
A7
→
FORMAT
FS[3–2]
VEC
FS[1–0]
Status Register
+ 0x04
Program Counter [31:0]
F
Freescale Semiconductor, Inc.
n
.