11-20
ColdFire CF4e Core User’s Manual
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Programming Model
Table 11-14 describes DBMR
n
fields.
DBRs support both aligned and misaligned references. Table 11-15 shows relationships
between processor address, access size, and location within the 32-bit data bus.
11.4.7 Program Counter Breakpoint/Mask Registers
(PBR, PBR1, PBR2, PBR3, PBMR)
Each PC breakpoint register (PBR, PBR1, PBR2, PBR3) defines an instruction address for
use as part of the trigger. These registers’ contents are compared with the processor’s
program counter register when the appropriate valid bit is set and TDR or XTDR are
configured appropriately. PBR bits are masked by setting corresponding PBMR bits.
Results are compared with the processor’s program counter register, as defined in TDR or
XTDR. PBR1–PBR3 are not masked. Figure 11-11 shows the PC breakpoint register.
Table 11-13. DBR
n
Field Descriptions
Bits
Name
Description
31–0
Data
Data breakpoint value. Contains the value to be compared with the data value from the processor’s
local bus as a breakpoint trigger.
Table 11-14. DBMR
n
Field Descriptions
Bits
Name
Description
31–0
Mask
Data breakpoint mask. The 32-bit mask for the data breakpoint trigger. Clearing a DBR
n
bit allows
the corresponding DBR
n
bit to be compared to the appropriate bit of the processor’s local data bus.
Setting a DBMR
n
bit causes that bit to be ignored.
Table 11-15. Access Size and Operand Data Location
A[1:0]
Access Size
Operand Location
00
Byte
D[31:24]
01
Byte
D[23:16]
10
Byte
D[15:8]
11
Byte
D[7:0]
0x
Word
D[31:16]
1x
Word
D[15:0]
xx
Longword
D[31:0]
F
Freescale Semiconductor, Inc.
n
.