
CONTENTS
Paragraph
Number
Title
Page
Number
Contents
xiii
12.2.3
12.2.4
12.2.4.1
12.2.4.2
12.2.4.3
12.2.4.4
12.3
12.3.1
12.3.2
12.3.3
12.3.4
12.3.5
12.3.5.1
12.3.6
12.3.6.1
12.3.6.2
12.3.7
12.3.8
12.3.9
12.3.9.1
12.3.10
12.4
12.5
12.5.1
Block Diagram.............................................................................................. 12-6
Timing........................................................................................................... 12-8
CF4eTW Testing of CF4e Core Inputs..................................................... 12-8
CF4eTW Testing of CF4e Core Outputs................................................ 12-11
CF4eTW Testing of Noncore Inputs ...................................................... 12-13
CF4eTW Testing of Noncore Outputs.................................................... 12-15
BIST................................................................................................................ 12-17
BIST Memory Controllers.......................................................................... 12-18
BIST Core Ports.......................................................................................... 12-19
Power Analysis........................................................................................... 12-20
Staging of Memories................................................................................... 12-20
Testing Algorithms..................................................................................... 12-21
March C+ Algorithm .............................................................................. 12-21
ROM BIST Algorithm................................................................................ 12-22
Modify BIST ROM Signature Script—Part 1........................................ 12-23
Modify BIST ROM Signature Script—Part 2........................................ 12-24
BIST Test Modes........................................................................................ 12-25
Memory Data Retention.............................................................................. 12-26
Timing......................................................................................................... 12-26
Memory Clock Determination................................................................ 12-27
Timing Diagrams........................................................................................ 12-28
Integration Connections.................................................................................. 12-32
Test Controller................................................................................................ 12-32
MTMOD[2:0] Encodings ........................................................................... 12-32
Appendix A
Core Interface Timing Characteristics
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.