Chapter 8. Local Memory
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8-29
ROM Overview
address registers (ROMBAR0 and ROMBAR1).
Note also that on-chip DMAs cannot access ROMs. The on-chip system configuration
allows concurrent core and DMA execution, where the core can reference code or data from
the internal SRAMs or caches while performing a DMA transfer.
8.6.2 ROM Programming Model
The ROM programming model consists of ROMBAR0 and ROMBAR1.
8.6.2.1 ROM Base Address Registers (ROMBAR0/ROMBAR1)
The ROM modules are configured through the ROMBARs, shown in Figure 8-10.
Each ROMBAR holds the base address of the ROM.
The MOVEC instruction provides write-only access to this register from the
processor.
Each ROMBAR
can be read or written from the debug module in a similar manner.
All undefined ROMBAR bits are reserved. These bits are ignored during writes to
the ROMBAR and return zeros when read from the debug module.
The initial state of the valid bit (V) is controlled by the value of a core input pin. If
the kromvldrst input is asserted at reset, the contents of the ROMBAR is forced to
0x0000_0121. This defines a valid ROM memory, based at address 0,
write-protected with the CPU space/interrupt acknowledge accesses masked. If
kromvldrst is negated, ROMBAR
n
[V] is cleared by reset, disabling the ROM
module.
ROMBAR
n
fields are described in detail in Table 8-24.
31
9
8
6
5
4
3
2
1
0
Field
BA
WP D/I
—
C/I
SC SD UC UD
V
Reset
—
00
—
—
—
—
—
x
1
R/W
W for CPU; R/W for debug
Address
CPU space + 0xC00 (ROMBAR0), 0xC01 (ROMBAR1
1 If kromvldrst is asserted at reset, the contents of the ROMBAR is forced to 0x0000_0121. This defines a valid ROM
memory, based at address 0, write-protected with the CPU space/interrupt acknowledge accesses masked. If
kromvldrst is negated, the valid bit is cleared by reset, disabling the ROM module.
Figure 8-10. ROM Base Address Registers (ROMBAR0/ROMBAR1)
F
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n
.