
Chapter 1. Introduction
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Chapter 1
Introduction
This section is an overview of the CF4e ColdFire microprocessor core. The CF4e
implementation of the Version 4 (V4) core includes the floating-point unit (FPU), enhanced
multiply-accumulate unit (EMAC), and memory management unit (MMU) that are defined
as optional in the V4 architecture.
1.1 Core Overview
The V4 core includes a Harvard memory architecture, branch cache acceleration logic, and
limited superscalar dual-instruction issue capabilities. The V4 core provides 1.54
Dhrystone 2.1 MIPS per MHz.
1.2 Features
The CF4e includes the following features defined as optional in the V4 core architecture:
Floating-point unit (FPU)
Virtual memory management unit (MMU)
Enhanced multiply-accumulate unit (EMAC) for increased signal processing
functionality plus backward code compatibility with the MAC unit of previous
ColdFire processors
V4 architecture features are defined as follows:
Variable-length RISC, clock-multiplied core
Revision B of the ColdFire instruction set architecture (ISA_B) providing new
instructions to improve performance and code density
Two independent, decoupled pipelines—four-stage instruction fetch pipeline (IFP)
and five-stage operand execution pipeline (OEP) for increased performance.
Ten-instruction, FIFO buffer decouples the IFP and OEP
Limited superscalar design approaches dual-issue performance with the cost of a
scalar execution pipeline
Two-level branch acceleration mechanism with a branch cache plus a prediction
table for increased performance of conditional Bcc instructions
32-bit address bus supporting 4 Gbytes of linear address space
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